Integrated circuits are generally tested by automated test equipment (ATE) to verify that the integrated circuit actually does what it was intended to do. A designer of the integrated circuit defines an input stimulus and corresponding expected output. The ATE provides the input stimulus to a tested integrated circuit, generally referred to as a device under test (DUT), and verifies that the resulting output from the DUT is substantially the same as expected.
Current integrated circuits are very complex and operate at very high speeds. The testing is therefore very demanding and not always can available ATEs provide an input stimulus operating the DUT in the simplest workable manner.
U.S. Pat. No. 8,156,396 to Gazounaud, which is incorporated herein by reference in its entirety, describes an ATE system with increased data rate of the ATE, by delegating processing tasks to multiple test components.
U.S. Pat. No. 6,978,410 to Parnas, which is incorporated herein by reference in its entirety, describes pin multiplexing to overcome ATE constraints.
U.S. Pat. No. 6,067,652 to Fusco et al., which is incorporated herein by reference in its entirety, describes a verification module which ensures that the input, output and bidirectional signal waveform formats of a designed test, are compatible with a targeted ATE. In addition, a translation module generates tester-compatible input stimulus files.
US patent publication 2015/0137838 to Lin et al., which is incorporated herein by reference in its entirety, describes a test system with edge steering.
US patent publication 2015/0137838 to Thiruvengadam et al., which is incorporated herein by reference in its entirety, describes a system that generates a strobe signal with a triggering edge that triggers a write, and a trailing edge that is modulated by adjusting the duty cycle of the strobe signal.